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* Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 125ps (max) High speed propagat.

* Clock distribution FUNCTIONAL BLOCK DIAGRAM GL G OUTPUT CONTROL Q1 Q1 PD OUTPUT CONTROL Q2 Q2 A1 A1 1 OUT.

The IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution n.

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